1. Field of the Invention
The present invention relates to a method for producing a resistive random access memory and, more particularly, to a method for producing a resistive random access memory which provides dual ion effects.
2. Description of the Related Art
Memories have been widely used in various electronic products. Due to the increasing need of data storage, the demands of the capacities and performances of the memories become higher and higher. Among various memory elements, resistive random access memories (RRAMs) have an extremely low operating voltage, an extremely high read/write speed, and highly miniaturization of the element size and, thus, may replace the conventional flash memories and dynamic random access memories (DRAMs) as the main stream of memory elements of the next generation.
FIG. 1 is a perspective view of a conventional resistive random access memory 9 for complementary resistive switches (CRS). The conventional resistive random access memory 9 includes a first metal layer 91, a first resistive switching layer 92, a second metal layer 93, a second resistive switching layer 94, and a third metal layer 95. The first resistive switching layer 92 is formed by silicon oxide and is located between the first metal layer 91 and the second metal layer 93. The second resistive switching layer 94 is formed by silicon oxide and is located between the second metal layer 93 and the third metal layer 95. A metal/insulator/metal/insulator/metal (MIMIM) structure is, thus, formed. Such a structure is obtained by reverse docking of two resistive random access memory elements of a metal/insulator/metal (MIM) structure. An electric field can be created to drive oxygen ions in the first and second resistive switching layers 92 and 94 to react with metal filaments to thereby undergo an oxidation/reduction reaction, forming a low resistance state (LRS) or a high resistance state (HRS) for storing data.
When a positive bias or a negative bias is applied to the conventional resistive random access memory 9 for complementary resistive switches, one of the two resistive random access memory elements undergoes a setting procedure, and the other undergoes a resetting procedure. By the asymmetry of the setting voltage and the resetting voltage respectively of the two resistive random access memory elements, a memory identification window W (FIG. 2) can be generated in the current-voltage curve to fix the sneak current of an integrated circuit of the resistive random access memory, an example of which is shown by Dirk J. Wouters, Leqi Zhang, Andrea Fantini, Robin Degraeve, Ludovic Goux, Yang Y. Chen, Bogdan Govoreanu, Gouri S. Kar, Guido V. Groeseneken, and Malgorzata Jurczak (“Analysis of Complementary RRAM Switching”, IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 8, AUGUST 2012). However, the resistive random access memory 9 for complementary resistive switches requires formation of a five-layer (MIMIM) structure, which involves complicated production process and which is difficult to reduce the production costs.
Thus, improvement to the conventional techniques is required for enhancing the utility.